Intel Corporation has published details on a new extension to the well-known x86 instruction set, due in the near future. Apparently the US company works on 512-bit AVX instructions that will first debut in the Xeon Phi “Knights Landing” co-processors and later in future microprocessors. The new instructions will allow for a significant performance boost when working with SIMD data since they will enable processing of two times as many data chunks at the same time when compared to the current AVX/AVX2 instruction sets.
Apart from the obvious performance gains AVX-512 will offer developers unprecedented flexibility. The instructions consist of 32 vector registers with each of them being 512 bits wide, which means programmers can use eight double-precision or sixteen single-precision floating point numbers or eight 64-bit integers or sixteen 32-bit integers within the 512-bit vectors. The new instructions will allow a large number of operations on data such as embedded rounding controls, embedded broadcast, high-speed math instructions, compact representation of large displacement values and others. A major improvement over older SIMD instruction sets is that AVX and AVX-512 instructions can be mixed without a penalty unlike, for example, SSE and AVX.
According to Intel the first AVX-512-enabled processors will appear in 2014 or maybe a bit later – sometime in 2015.
Source: Intel